Booth&#39;s multiplier

ABSTRACT

In Booth&#39;s method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP i  (Y i , Y i+1 , Y i+2 ); partial products PD i  are formed separately in sequence by multiplying X by each of decoded partial multiplier values V pp  decoded in accordance with Booth theory; and all the partial products PD i  are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and V pp  are formed simultaneously in sequence and added to obtain a partial product sum PS i , and all the two partial product sums are accumulatively added to obtain a final result.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multiplier which can attain a highspeed multiplication operation on the basis of a relatively simplecircuit configuration.

2. Description of the Prior Art

Multipliers can be classified into roughly two, parallel and series,multipliers. In the series multiplier, the product of a multiplicand anda multiplier can be obtained in such a way that a multiplicand ismultiplied by a multiplier digit by digit, the multiplication processingfor each digit is shifted in sequence, and the multiplied results of alldigits are accumulatively added.

More specifically, in the series multiplier, a partial product is formedby multiplying a multiplicand by a multiplier digit by digit, that is,bit by bit in a binary computer. For instance, in the case where thenumbers of bits of a multiplier and a multiplicand are both 32 bits (32bits×32 bits), the product can be obtained by forming 32 partialproducts of a 32-bit multiplicand and a one-bit multiplier and byaccumulatively adding these 32 partial products. In the seriesmultiplier, each partial product is formed for each digit of themultiplier in sequence and then accumulatively added in sequence in theorder of the partial product formation. Therefore, one partial productforming circuit for forming many partial products and one adder circuitfor sequentially and accumulatively adding these partial products arerequired. However, the calculation speed is slow.

In contrast with this, in the parallel multiplier, each partial productof a multiplicand and a multiplier is formed simultaneously for eachdigit, and all the partial products formed simultaneously are added alsosimultaneously, so that the calculation speed is very high. However,since all the partial products are formed and added simultaneously, inthe case of a 32-bit multiplication, for instance, 32 partial productforming circuits and 32 adders for adding 32 partial products arenecessary.

In addition, Booth's algorithm method is known as a method ofmultiplying a multiplicand by a multiplier in series and parallelfashion. In the series multiplier, multiplication is processed for eachbit of a multiplier to form 32 partial products, for instance. Incontrast with this, in this Booth method, partial products are formedevery three bits of a multiplier and further one bit of these three bitsis overlapped upon one of other adjacent three bits. As a result, in thecase of 32 bit multiplication, only 16 partial products are formed. The16 partial products are added to obtain a multiplied result. In thisBooth method, since 16 partial products are formed in sequence every 3bits of the multiplicand and then these partial products are added insequence, only one partial product forming circuit and one adder arerequired as in the series multiplier, and advantageously the calculationspeed thereof is two times higher than that of the series multiplier.

As explained above, although the series multiplier is simple andeconomical from the standpoint of circuit configuration, there exists aproblem in that the calculation speed is very slow. Although theparallel multiplier is high in speed, there exists a problem in thatmany partial product forming circuits and adders are required, so thatthe cost is high and the space occupied by the circuit is voluminous.Further, in the Booth's algorithm multiplier belonging to between seriesand parallel circuits, although the speed is relatively high in spite ofa relatively simple circuit configuration, the calculation speed isstill slow as compared with that of the parallel multiplier. Forinstance, although the parallel multiplier can form and add partialproducts simultaneously, in the Booth method, 16 processing steps arerequired to process a multiplication of 32 bits, and therefore therestill exists a problem in that the multiplication speed is 16 timesslower than that of the parallel multipliers.

SUMMARY OF THE INVENTION

With these problems in mind, therefore, it is the primary object of thepresent invention to provide a high speed multiplier of a relativelysimple circuit configuration.

To achieve the above-mentioned object, the multiplier according to thepresent invention comprises (a) partial multiplier forming means forforming a plurality of partial multipliers by dividing a multiplier intoplural segments having plural predetermined digits; (b) partial productsum forming means for forming a partial product sum by adding twopartial products formed by simultaneously multiplying a multiplicand byeach of two partial multipliers of a plurality of the divided partialmultipliers; (c) accumulative addition control means for controllingsaid partial product sum forming means so that partial product sumsformed by said partial product sum forming means can sequentially beformed for all the partial multipliers in the same way as for the abovetwo partial multipliers, and for accumulatively adding all the formedpartial product sums.

To achieve the above-mentioned object, the method of multiplying amultiplicand X by a multiplier Y according to the present inventioncomprises the following steps of: (a) dividing plural bits of themultiplier Y into a plurality of partial multipliers PPi (Y_(i),Y_(i+1), Y_(i+2)) of 3 bits; (b) simultaneously decoding at least twopartial multipliers in accordance with Booth's theory to generate atleast two decoded partial multiplier value Vpp; (c) simultaneouslycalculating at least two partial products PDi of the two decoded partialmultiplier values Vpp and each bit of the multiplicand X; (d) adding thesimultaneously calculated at least two partial products PDi to obtain apartial product sum PSi; (e) sequentially repeating the above steps from(a) to (d) for all the remaining partial multipliers by shifting each ofbits of the multiplier; and (f) accumulatively adding all the calculatedpartial product sums.

In the Booth method, a multiplier Y is divided into plural partialmultiplier PPi (Y_(i), Y_(i+1), Y_(i+2)); partial products PDi areformed separately in sequence by multiplying a multiplicand X by each ofdecoded partial multiplier values V_(pp) decoded in accordance withBooth theory; and all the partial products PPi are added to obtain theproducts. In the present invention, however, in order to increase themultiplication processing speed twice in spite of a relatively simplecircuit configuration, two partial products of the multiplicand X andthe decoded partial multiplier values Vpp are calculated simultaneouslyand added to obtain a partial product sum PSi, and all the product sumsthus obtained are accumulatively added to obtain a final result.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the multiplier according to the presentinvention will be more clearly appreciated from the followingdescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 is a block diagram of an embodiment of the multiplier accordingto the present invention;

FIG. 2 is a block diagram of a CPU to which the multiplier shown in FIG.1 is applied;

FIGS. 3(a) and 3(b) are block diagrams of partial product generatingsections incorporated in the multiplier shown in FIG. 1;

FIGS. 4 to 8 are diagrams for assistance in explaining the principle andthe operation of the multiplier shown in FIG. 1; and

FIG. 9 is a timing chart for assistance in explaining the operation ofthe multiplier shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

With reference to the attached drawings, an embodiment of the presentinvention will be described.

In FIG. 1, the multiplier of the present invention comprises a partialproduct multiplication section (MUL) 1 for forming two partial productsand adding these two partial products to obtain a partial product sum,an arithmetic and logical unit (ALU) 3 for accumulatively adding thepartial product sum, and a barrel shifter section 5 for shifting amultiplier 4 bits by 4 bits (shifting out from the least significant bit(LSB) side) and transferring the shifted-out 4 bits to the partialproduct multiplication section 1.

The above three units or sections are connected to each other via twobuses 7 and 9, and the multiplication operation can be attained inaccordance with pipe line processing method through these bus lines 7and 9.

The multiplier shown in FIG. 1 is used for achieving 32-bitmultiplication operations, and incorporated in a 32-bit microprocessor(CPU) as shown in FIG. 2. In use, the multiplier is connected to the CPUvia the buses 7 and 9 to achieve the pipe line processing. This CPUshown in FIG. 2 is connected to a storage unit (not shown) via anaddress bus interface 11 and a data bus interface 13 to readinstructions such as multiplication instructions from the storage unitunder the control of a memory management unit 15. The read instructionis set via the data bus interface 13 to a prefetch unit 17 and thendecoded by an instruction decoder 19. The decoded instruction is fed viaa pipe line controller 21 to other sections (such as MUL 1, SHT 5, andALU 3 shown in FIGS. 1 and 2) under the control of the pipe linecontroller 21. Further, this CPU is provided with a CPU flag controller25 and a register file 27.

With reference to FIG. 1 again, a MRφ register 31 for storing a 32-bitmultiplicand X is connected to the partial product multiplicationsection MUL 1 to supply the multiplicand X to the MUL 1. Thismultiplicand X is set to the MRφ register 31 via the bus 7 under thecontrol of the pipe line controller 21. Further, a SRφ register 33 forstoring a 32-bit multiplier Y is connected to the shifter section 5 tosupply a multiplier Y.

To the input of the ALU 3, an ARφ register 35 and an AR1 register 37 areconnected. To the ARφ register 35, an output of the ALU 3 is set via aselector 39. The output of the ALU3 is an accumulatively added result ofpartial product sums as described later. To the AR1 register 37, a newpartial product sum is set from the partial product multiplicationsection 1. The sum of both the inputs (accumulative partial product sumand new partial product sum) are calculated by the ALU 3. Further, apart of the accumulative partial product sum outputted from the ALU 3 (4lower significant bits) is supplied to the SRφ register 33, and theremaining bits are supplied to the ARφ register 35 via the selector 39.

A multiplier Y set to the SRφ register 33 is supplied to the partialproduct multiplication section 1, 4 bits (lower significant) by 4 bits.The sum of these two partial products of the 4 lower significant bitsand CY is calculated by the partial product multiplication section 1.The remaining 28 bits set in the SRφ register 33 are shifted rightward,that is, toward the LSD (the least significant digit) side 4 bits by 4bits via the shifter section 5 and the bus 9, and are set again to theSRφ register 33 for the preparation for supplying the 4 lower bits tothe partial product multiplication section 1. Further, the first bit ofthe result shifted out rightward 4 bits by 4 bits is supplied as a CYbit from the shifter section 5 to the partial product multiplicationsection 1.

This CY bit is "0" at the first partial product calculation as describedlater.

FIGS. 3(a) and 3(b) are more detailed block diagram of the partialproduct multiplication section 1, which includes two partial productgenerators 41 and 43 for simultaneously generating two partial productsand an adder 45 for simultaneously adding two partial products outputtedfrom these two partial product generators 41 and 43. Without generatingpartial products for each bit of a 32-bit multiplier Y as in the seriesmultiplier, the partial product generators 41 and 43 form a plurality ofpartial multipliers (CY, Y_(i), Y_(i+1), Y_(i+2), Y_(i+3)) by dividingthe multiplier Y 3 bits by 3 bits beginning from the least significantdigit, and calculates the partial products of each 3-bit partialmultiplier (CY, Y_(i), Y_(i+1)), (Y_(i+1), Y_(i+2), Y_(i+3)) and the32-bit multiplicand X by applying the Booth method. Therefore, thepartial product multiplication section 1 receives partial multiplier(CY, Y_(i), Y_(i+1), Y_(i+2), Y_(i+3)) from the SRo register 33, andBarrel shifter and put. To obtain partial products on the basis of thepartial multiplier (CY, Y_(i), Y_(i+1)), (Y_(i+1), Y_(i+2), Y_(i+3)) inpartial product mode or in the Booth method (as described later), thereare provided two partial product mode generators 47 and 49 forgenerating decoded partial multiplier values to be decided on the basisof two 3-bit partial multipliers. The outputs of the partial productmode generators 47 and 49 are supplied to the partial product generators41 and 43.

In the multiplier of the present invention, the partial productmultiplication section 1 simultaneously forms two partial products oftwo 3-bit partial multipliers (CY, Y_(i), Y_(i+1)), (Y_(i+1), Y_(i+2),Y_(i+3)) and a multiplicand X in accordance with Booth method, andaccumulatively adds these two partial product sum in sequence to obtaina product. The above-mentioned principle will be described hereinbelowin further detail with reference to FIGS. 4 to 8.

In the usual situation, when a multiplication is effected manually, amultiplicand X is written on the upper side; a multiplier Y is writtenunder and in parallel to the X; a line is drawn under the X and Y,partial products obtained by multiplying X by each digit of Y arewritten in sequence under the line; and all the partial products areadded. In the Booth method, instead of obtaining partial products foreach digit of the multiplier Y, a multiplier Y is divided 3 bits(digits) by 3 bits (digits) to effect plural partial multiplicationscorresponding to the divided multiplier of 3 bits; the multiplicand X ismultiplied by the 3-bit divided multipliers to obtain partial products;and the final product is obtained by adding these partial products. Whenobtaining partial products of 3-bit divided partial multipliers of amultiplier Y and a multiplicand X, the binary values of 3-bit partialmultipliers PPi (CY, Y_(i), Y_(i+1)) or (Y_(i+1), Y_(i+2), Y_(i+3)) arenot used, as they are, for multiplication to the multiplicand X, butpartial multiplier values V_(pp) decoded in accordance with the Booth'stheory are used.

FIG. 4 shows an example of the Booth multiplication method, in whichpartial multiplier PPi, decoded partial multiplier values Vpp andpartial products PDi of a multiplicand X=13 (00001101 in binary) and amultiplier Y=36 (00100100 in binary) are arranged in order.

In order to form partial multipliers PPi of the multiplier Y=Y₇, Y₆, Y₅,Y₄, Y₃, Y₂, Y₁, and Y₀ (=00100100) in 3-bit unit, an additional one bitY₋₁ of "0" is added below the least significant bit Y_(O) as a CY bit; afirst partial multiplier PP₁ is formed by three bits Y₋₁, Y₀ and Y₁ ; asecond partial multiplier PP₂ is formed by three bits Y₁, Y₂ and Y₃ ;and third and fourth partial multipliers PP₃ and PP₄ are formed in thesame way. On the basis of these bits, partial products PDi (i.e. PD₁,PD₂, PD₃ and PD₄) are obtained by multiplying the multiplicand X by eachpartial multiplier PPi, and a product 468 (0000000 11101 0100 in binary)can be obtained by adding these partial products PDi. Although thepartial multipliers PPi are formed 3 bits by 3 bits, since one of threebits is overlapped, the number of bits is reduced to 2 bits in practice.In the above multiplication example of 8 bits, 4 partial multipliers PPiare formed; four partial products PDi are formed for these four partialmultiplier PPi, respectively. Further, in the case of 32-bitmultiplication (i.e. a multiplicand X and a multiplier Y are each 32bits), 16 partial products PDi are to be formed.

FIG. 5 shows partial multipliers PP₁, PP₂, PP₃ -PP₁₆ of a multiplierYI_(i) in 32-bit multiplication. In the Booth method, 16 partialmultipliers PPi are formed to a 32-bit multiplicand X. In correspondenceto these 16 partial multipliers PPi, 16 partial products PDi are formed,and these partial products PDi are added in sequence. Further, Y₋₁ of"0" is added to below Y₀ to form the partial multiplier PP₁, and theleast significant partial multiplier PPi is composed of Y₋₁, Y₀, and Y₁.

In the present invention, however, the 16 partial products PD_(i) arenot formed separately, but partial products PD_(i) are formed two by twoat the same time.

In more detail, as shown in FIG. 5, two partial products PD_(i) of PP1and PP2, PP3 and PP4, PP5 and PP6, PP7 and PP8, PP9 and PP10, PP11 andPP12, PP13 and PP14, and PP15 and PP16 are formed simultaneously.

The two partial products PD_(i) formed simultaneously are added 8 timesto form 8 partial product sums PS_(i). The product can be obtained byadding 8 partial product sums in sequence.

In this Booth method, as shown in FIG. 3, when the partial productPD_(i) are formed by multiplying the multiplicand X by the partialmultiplier PP_(i), the partial multiplier PP_(i) is not used as anumerical value, but decoded partial multipliers values Vpp obtained bydecoding the partial multiplier PP_(i) through the partial product modegenerators 47 and 49 are used. Since the partial multiplier PP_(i) isformed with 3 bits, although there exist 8 statues of 000, 001,010,-111, the decoded partial multiplier values V_(pp) as shown in FIG.5 are used for the partial multiplier PP_(i) corresponding to the 8states; and the partial products PD_(i) can be formed by multiplying themultiplicand X by the decoded partial multiplier value V_(pp). In moredetail, as well understood by the table shown in FIG. 5, the decodedpartial multiplier value V_(pp) is 0 when the partial multiplier PP_(i)is 000 and 111,+1 when PP_(i) is 001 and 010,+2 when PP_(i) is 011, -2when PP_(i) is 100, and -1 when PP_(i) is 101 and 110. Further, FIG. 4is a table showing the relationship between the decoded partialmultiplier value V_(pp) and each partial multiplier PP_(i) of themultiplier Y.

Booth algorithm and the decoded partial multiplier values V_(pp) will bedescribed hereinbelow.

Here, if a multiplicand X and a multiplier Y (n-bit numbers including asign) are expressed as X=X_(n-1), X_(n-2) -X₀, and Y=Y_(n-1),Y_(n-2),-Y₀, respectively, the both X and Y can be expressed as ##EQU1##if the number of digits of the multiplier Y is an even number and Y₀ =0,the multiplier Y can be expressed as ##EQU2##

As a result, the product P of the multiplicand X and the multiplier Ycan be expressed as ##EQU3##

As understood by this expression (5), the number of partial products Pof multiplicand X and multiplier Y is n/2. Further, the calculatedvalues (Y_(2i), Y_(2i+1), -2 Y_(2i+2)) shown by parentheses indicatesthe decoded partial multiplier value V_(pp), that is, 0,±1, and ±2 asshown in FIG. 4. The multiplication operation given by the expression(5) is the Booth algorithm when executed, in which partial productsPD_(i) of the decoded partial multiplier value V_(pp) and themultiplicand X of n/2 are required. FIG. 5 shows the partial multipliersPP₁ to PP₁₆ and the decoded partial multiplier values V_(pp) when themultiplier Y is 32 bits. Further, in FIG. 5, the decoded partialmultiplier V_(pp) =0 indicates that the multiplicand X is multiplied by"0"; V_(pp) +1 indicates that the multiplicand X is kept as it is;V_(pp) =-1 indicates that the multiplicand X is changed into a negativenumber; V_(pp) =+2 indicates that the multiplicand X is multiplied bytwo, that is, X is shifted one bit leftword; and V_(pp) =-2 indicatesthat the multiplicand X is multiplied by two and further changed into anegative number.

In the partial product multiplication section 1 shown in FIG. 3(a), thepartial decoded multiplier values V_(pp) corresponding to each partialmultiplier PP_(i) are formed by the partial product mode generators Ydee47 and 49. The partial products PD_(i) of the decoded partial multipliervalue V_(pp) and the multiplicand X are formed two by two simultaneouslyby the partial product generators 41 and 43. These two partial productsPD_(i) are added by the adder 45 to output the partial product sumPS_(i). To obtain the partial product sum PS_(i) by adding a firstpartial product PD_(i) from the partial product generator 41 and asecond partial product PD_(i) from the partial product generator 43through the adder 45, as shown in FIGS. 4 and 5, the partial product sumPS_(i) is calculated by shifting the two partial product sums PS_(i) 2bits by 2 bits and by adding them through the adder 45. Here, themultiplicand X supplied to the adder 45 is of 32 bits, and the maximumnumber of the decoded partial multiplier value V_(pp) is 2. This is toshift the multiplicand X one bit rightward. Further, two bits areshifted for addition of the partial product sum PD_(i), and further onebit is necessary for a sign bit, so that the output data from the adder45 is of 36 bits as shown in FIG. 3 (b).

As described above, the 32-bit partial product sum PS_(i) calculated bythe partial product multiplication section 1 is set to the AR1 register37. The sums PS_(i) are further accumulatively added to the accumulativeresult of the 36-bit partial product SUM PS_(i) stored in the ARφregister 35 by the ALU3. Further, at the start of multiplication, theARφ register 35 is set to "0".

FIG. 6 explains the calculation of partial product sum PS_(i) in thepartial product multiplication section 1 and the accumulative additionprocessing in the ALU3.

As understood in FIG. 6, at the first-cycle, the adder 45 of the partialproduct multiplication section 1 adds a first partial product PD₁ and asecond partial product PD₂, and the first partial product sum PS₁ issupplied to the ALU3 via the AR1 register 37. This first partial productsum PS1 is added to the accumulation result of the ARφ register 35 whichis initially set to "0", so that a 36-bit accumulated result isoutputted from the ALU3. Since 4 lower significant bits of a 36-bitaccumulated result have already been decided by the lst cyclemultiplication, these bits are supplied to the SRφ register 33 as thehigh significant bits. The accumulated result of the remaining 32higher-significant bits outputted from the ALU3 is set to the ARφregister 35 via the selector 39 as the 32 lower significant bits. A signexpansion bit is set to the 4 high significant bits of the ARφ register35, so that the ARφ register 35 becomes 36 bits. This 36-bit accumulatedresult is supplied again from the ARφ register 35 to the ALU3, and addedto the second partial product sum PS₂ which is the second calculationresult in the partial product multiplication section 1. Further, 4 bitsof the 36-bit accumulated result from the ALU3 is supplied to the SRφregister 33 as the determined second-cycle 4-bits in the same way, andthe remaining 32-bits are supplied to the ALU3 via a selector 39together with the extended 4-bit sign. In the same way, the abovecalculation continues until the eighth partial product sum PS₈ obtainedby adding the 15th partial product PD₁₅ and the 16th partial product sumPS₁₆ is accumulatively added to the previous accumulated result by theALU3.

To the partial product multiplication section 1, 4 bits constituting twopartial multipliers PP_(i) are supplied from the SRo register 33 insequence. In synchronism with the one-cycle operation of the particalproduct multiplication section 1 as described above, 4 highersignificant bits of the determined accumulated result are supplied tothe 4 higher-significant bits of the SRφ Register 33 in sequence. Insynchronism with these, 4 lower significant bits of the SRφ Register 33are supplied in sequence to the partial product multiplication section1.

FIGS. 7 and 8 show the relationship between the shift operation of theshifter section 5 to the SRφ register 33 and the partial multiplierPP_(i). As shown in the drawings, the multiplier Y (=Y₀, Y₁, Y₂ . . .Y₂₉, Y₃₀, Y₃₁) initially set to the SRφ register 33 includes the leastsignificant bit of "0" which is set as a CY bit. The 4 lower significantbits including the CY bit are divided into the first partial multiplierPP_(l) (cy, Y₀, y_(l)) and the second partial multiplier PP₂ (Y₁, Y₂,Y₃), and supplied to the partial product mode generators 47 and 49 ofthe partial product multiplication section 1, respectively. On the basisof these, the first multiplication is achieved. Upon completion of thefirst multiplication, the stored value of the SRφ register 33 is shiftedby 4 bits via the shifter section 5 and the bus 9, so that the 4 lowersignificant bits including the CY bit (Y₃, Y₄, Y₅, Y₆) are set.

As described above, the 4 lower significant bits determined on the basisof the accumulatively added result are supplied from the ALU3 to the 4higher significant bits of the SRφ register 33 in order to achieve thesecond multiplication. In the same way, the above operation is repeated.In the case of the final eighth multiplication, the 4 most significantbits of the multiplicant Y are shifted to the 4 lower significant bits,and the determined accumulated result is set to the remaining 28 highersignificant bits. When the 8th multiplication has been completed, the 32lower significant bits of the product P are set to the SRφ register 33,and the 32 higher significant bits of the product P are set to the ARφregister 35.

As described above, in the embodiment of the present invention, twopartial products PDi are added simultaneously to obtain partial productsums PS_(i) in the partial product multiplication section 1; thesepartial product sums PS_(i) are accumulatively added in sequence by theALu3. To obtain the partial product sums PS_(i) and the accumulativeproduct addition, the partial multipliers PP_(i) of the multiplier Y areshifted in sequence in the SRφ register 33 and the shifter section 5 forsequential multiplication operation. Further in order to achieve thesequential operation between the partial product multiplication section1, the ALU3 and the shifter section 5, the pipe line method is adoptedthrough the buses 7 and 9.

Further, although multiplication is achieved on the basis of the pipeline processing in the partial product multiplication section 1, theALU3, and the hsifter 5, since multiplication is executed under thepresence of signs in the ordinary Booth algorithm, correction isrequired in the case of the absence of signs. This correction methodwill be described below. If multiplicands and multipliers having nosigns are designated as X*, Y* and those having signs are designated asX, Y, the following relation can be obtained between the two as follows:

    X * Y *=X·Y+2 n Y.sub.n-1 ·X+2 n X.sub.n-1 ·Y (6)

Therefore, to correct the results of multiplicand X and multiplier Yhaving signs into those having no signs, 2nY_(n-1) ·X and 2nX_(n-1) ·Yare added. This correction is made by means of the ALU. With respect tothe correction of 2nY_(n-1) ·X, X is added to the result when the mostsignificant bit of the multiplier Y is "1", while "0" is added (nothingis made) when the most significant bit thereof is "0". With respect tothe correction of 2nX_(n-1) Y, Y is added to the result when the mostsignificant bit of the multiplicand X is "1", while "0" is added(nothing is made) when the most significant bit thereof is "0".

To further clarify the above operation, the multiplication of 8-bitmultiplicand X and 8-bit multiplier Y will be described with referenceto the pipe line processing timing chart shown in FIG. 9.

In FIG. 9, each partial product sum PS_(i), each accumulative additionoperation, etc. are achieved for each cycle as designated by numeralsshown at the uppermost position in FIG. 9. The multiplicand X and themultiplier Y are designated as X₇, X₆, --X₁, X₀ and Y₇, Y₆ --Y₁, Y₀,respectively. The output of the SRφ register 33 is expressed by SRo; theoutput of the shifter section 5 is expressed as SHF; the output of thepartial product multiplication section 1 is designated as MUL; and theoutput of the ALU3 is designated as ALU. In the SRφ, "0000Y₇ to Y₄ "indicates that Y₇ to Y₀ are shifted by 4 bits. In MUL, "X·Y<3:0>"indicates that 4 bits (Y₃ to Y₀) and CY bit of the multiplier Y aredecoded in value to form partial products PD1 and 2 and the partialproduct sum PS is obtained. Further, in the SRφ, the 4 lower significantbits P₃ to P₀ of the accumulative result determined by the ALU3 as shownin the fourth cycle, for instance, are supplied to the 4 highersignificant bits; these bits are further shifted by 4 bits and thesucceeding determined result is supplied in the fifth cycle as indicatedby P₇ to P₀. In the ALU, the first accumulative addition "O+X·Y<3:0>" isachieved in the third cycle, and the second accumulative addition"X·Y<3:0>+X·Y <7:4> is achieved in the fourth cycle.

First, the multiplicand X and the multiplier Y are supplied via thebuses 7 and 9, respectively in the first cycle, and set to the MRφregister 31 and the SRφ 33, respectively, in the second step. When themultiplier Y is set to the SRφ register 33, the 4 lower significant bitsof this multiplier Y are supplied to the partial product multiplicationsection 1; two decoded partial multiplier values V_(pp) decoded by thepartial product mode generators 47 and 49 of the partial productmultiplication section 1 are supplied to the partial product generators41 and 43, respectively to form two partial products PD_(i) ; and thesetwo partial products PD_(i) are added by the adder 45 to obtain thepartial product sum PS, that is, X. Y<3:0>. At the same time, themultiplier Y set to the SRφ register 33 is shifted by 4 bits through theshifter 5 as "0000 Y₇ to Y₄ ". As described above, in the second cycle,since the calculation of the partial product sums PS_(i) and the shiftoperation are achieved simultaneously, the multiplication speed isincreased.

In the third cycle, the multiplier Y shifted by the shifter section 5 isset to the SRφ register 33; the 4 lower significant bits of the shiftedmultiplier Y are supplied to the partial product multiplication section1 to calculate X . Y <7:4> of the partial product sum PS of these 4-bitsand the multiplicand X. Further, the multiplier Y set to the SRφregister 33 is further shifter by 4 bits through the shifter section 5so that the output of the shifter section 5 is "0000 0000"; and X .Y<3:0> of the partial product sum PS is obtained as the firstaccumulative addition in the ALU 3 and "0+X.Y<3:0>" is indicated. Sinceno previous accumulative addition exists in the initial operation, "0"is indicated.

When the output of the shifter section 5 is supplied to the SRo register33 in the third cycle, the 4 lower significant bits determined by thethird-cycle accumulative addition in the ALU 3 as described above aresupplied to the 4 higher significant bits of the SRo register 33 toobtain "P₃ to P_(o) 0000". Further, the value of this SRφ register 33 isshifted by the shifter section 5, so that the output of the shiftersection 5 is "0000 P₃ to P₀ ".

In the fourth cycle, since the calculation of the partial product sum PShas already been completed in the partial product multiplication Section1, no information exists in the MUL 1. Therefore, in the ALU3, thepartial product sum PS of X.Y<7:4> outputted from the partial productmultiplication section 1 is accumulatively added to the previousaccumulative addition result of X.Y<3:0> in the ALU3.

In the fifth cycle, the 4 lower significant bits determined on the basisof the fourth cycle accumulative addition in the ALU3 are supplied tothe 4 higher significant bits of the SRφ register 33, so that the SRφregister 33 is set to "P₇ to P₀ "; that is, the 8 lower significant bitsof this multiplication are set to the register 33. At this moment, theoperation has already been completed in the shifter section 5 and thepartial product multiplication section 1. Further, the 8 highersignificant bits of this multiplication are set to the ALU3. Further, ifcorrection is required to the calculated results, the correction ofY7.X+X.Y=S is made beginning from the most significant bit of themultiplier Y. As already explained, since the multiplication is madeunder the presence of signs in the Booth algorithm, when no sign exists,the conversion from the presence of sign to the absence of sign isnecessary for correction.

In the sixth cycle, the calculation of X₇ Y+S' is made beginning fromthe most significant bit of X when correction is required, and thecalculated result is transferred to a desired destination within thesame cycle.

Further, in the seventh cycle, the least significant multiplicationresult set to the SRφ register 33 is also transferred to a desireddestination.

The multiplier of the present invention is made up of these blocks ofthe partial product multiplication section 1, the ALU (arithmetic andlogical unit) 3 and the shifter section 5. Among these, the ALU3 and theshifter section 5 are usable in common with those already incorporatedin a microprocessor, and only the partial product multiplication section1 is newly required. Therefore, it is easy to integrate the multiplierwith a microprocessor LSI, and hardware is relatively small in volume,thus it being possible to realize a high-performance LSI.

In comparison between the parallel method and the pipe line method withrespect to the number of elements, 11,800 transistor elements arerequired in the parallel method, while 1,900 transistor elements arerequired in the pipe line method. Further, with respect to the number ofclocks, the parallel method requires 4 clocks, while the pipe linemethod requires 13 clocks.

As described above, according to the present invention, since a productis obtained in such a way that a multiplier is divided into somesegments including a predetermined number of bits (digits) to form aplurality of partial multipliers; a multiplicand is multiplied by eachof two partial multipliers of them to obtain two partial productssimultaneously; these two partial products are added to obtain partialproduct sums simultaneously; the above partial product sums are formedin sequence for all the partial multipliers; and all the partial productsums are accumulatively added in sequence.

Therefore, the processing speed is fairly high as compared with that ofthe series multiplication method; the number of hardware is very smallas compared with the parallel multiplication method; the processingspeed is roughly twice higher than that in the Booth method because twopartial products are added simultaneously. That is to say, it ispossible to achieve a multiplier which can attain a relativelyhigh-speed multiplication operation in spite of an economical circuitconfiguration.

What is claimed is:
 1. A Booth's multiplier comprising:(a) partialproduct multiplication means for simultaneously generating at least twopartial products of a multiplier including at least two bits divided insequence beginning from the least significant digit of the multiplierand a multiplicand and for calculating a sum of the at least two partialproducts; (b) calculating means for accumulatively adding the calculatedpartial product sums; and (c) shifter means for shifting the multiplierby the number of bits required to generate the plural partial productsand for transferring the bits of the multiplier to said multiplicationmeans whenever said multiplication means calculates one sum of thepartial products.
 2. The Booth'a multiplier as set forth in claim 1,wherein said partial product multiplication means comprises:(a) twopartial product mode forming means for each forming a decoded partialmultiplier value on the basis of a 3-bit partial multiplier inaccordance with Booth's algorithm; (b) two partial product generatingmeans for each generating a partial product of the decoded partialmultiplier value and the multiplicand; and (c) adder means for addingthe two partial products.
 3. The Booth's multiplier as set forth inclaim 2, wherein the partial products are obtained on the basis ofcalculations as listed below according to the value of a 3-bitmultiplier (Y_(i+2), Y_(i+1), Y_(i)), where X denotes a multiplicand: 4.The multiplier as set forth in claim 1, wherein the number r of thepartial products added by said multiplication means is

    2≦r<n/m

where n denotes the number of bits of the multiplier; and m denotes thenumber of bits included in respective bit groups.
 5. The Booth'smultiplier as set forth in claim 4, wherein each of the bit groups ismade up of three bits.
 6. The Booth's multiplier as set forth in claim5, wherein the 4 lower significant bits determined as an accumulatedresult of said calculating means are stored in the 4 higher significantbits of a multiplicant shifted rightward.
 7. The Booth's multiplier asset forth in claim 1, wherein the multiplication is effected inaccordance with Booth algorithm.
 8. The Booth's multiplier as set forthin claim 1, wherein the partial product calculation, the accumulativeaddition calculation and shifting calculation are processed in parallelin each of said partial product multiplication means, said calculatingmeans and shifting means.

    ______________________________________                                        Y.sub.i+2  Y.sub.i+1                                                                            Y.sub.i     CALCULATION                                     ______________________________________                                        0          0      0           0                                               0          0      1           +X                                              0          1      0           +X                                              0          1      1           +2 X                                            1          0      0           -2 X                                            1          0      1           -X                                              1          1      0           -X                                              1          1      1           0                                               ______________________________________                                    


9. A Booth's multiplier comprising:(a) partial multiplier forming meansfor forming a plurality of partial multiplier by dividing a multiplierinto plural segments having plural predetermined digits including oneoverlap bit for each partial multiplier; (b) partial product sum formingmeans for forming a partial product sum by adding two partial productsformed by simultaneously multiplying a multiplicand by each of twopartial multipliers of a plurality of the divided partial multipliers;and (c) accumulative addition control means for controlling said partialproduct sum forming means so that partial product sums formed by saidpartial product sum forming means can sequentially be formed for all thepartial multipliers in the same way as for the above two partialmultipliers, and for accumulatively adding all the formed partialproduct sums.
 10. A method of multiplying a multiplicand X by amultiplier Y, which comprises the following steps of: (a) dividingplural bits of the multiplier Y into a plurality of partial multipliersPP_(i) (Y_(i), Y_(i+1), Y_(i+2)) of 3 bits;(b) simultaneously decodingat least two partial multipliers in accordance with Booth's theory togenerate at least two decoded partial multiplier values V_(pp) ; (c)simultaneously calculating at least two partial products PD_(i) of thetwo decoded partial multiplier values V_(pp) and each bit of themultiplicand X; (d) adding the simultaneously calculated at least twopartial products PD_(i) to obtain a partial product sum PS_(i) ; (e)sequentially repeating the above steps from (a) to (d) for all theremaining partial multipliers by shifting each of bits of themultiplier; and (f) accumulatively adding all the calculated partialproduct sums.